• Description: The project is an OpenSPARC T1-based SoC which includes: – Full or reduced OpenSPARC T1 CPU core – OpenSPARC FPU – Bridge to connect the CPU and FPU to the Whisbone bus – Nor flash controller – UART – OpenCores ethernet controller – Bridges from Whishbone to Altera and Xilinx DRAM controllers The goal of this project is to perform the complete backend design of a OpenSPARC T1 microprocessor...
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