A CISC decoder is typically set up as a state machine. The machine reads the opcode field to determine what type of instruction it is, and where the other data values are. The instruction word is read in piece by piece, and decisions are made at each stage as to how the remainder of the instruction word will be read. One method to alleviate this is to use a decoded instruction cache, such that if an instruction is decoded once and stored in a cache, the next time it is fetched, the CPU can eliminate the need to re-decode it.
In this project the students will design a RISC CPU and implement a decoded instruction cache.
Project description:
In RISC processor the instruction decoder is typically a very simple device. As RISC instruction words are a fixed length, the positions of the fields are fixed, and processor reads in the entire instruction into the instruction register. We can decode an instruction, therefore, by simply separating the machine word in the instruction register into small parts using wire slices.
In CISC processor however, decoding an instruction word is much more difficult, and the increased complexity of the decoder is a common reason that people cite when they choose to use RISC over CISC in their designs.
A CISC decoder is typically set up as a state machine. The machine reads the opcode field to determine what type of instruction it is, and where the other data values are. The instruction word is read in piece by piece, and decisions are made at each stage as to how the remainder of the instruction word will be read.
One method to alleviate this is to use a decoded instruction cache, such that if an instruction is decoded once and stored in a cache, the next time it is fetched, the CPU can eliminate the need to re-decode it. This can save time and power. Since many computer codes contain loops, it is very likely that a current instruction is going to be repeated in the near future, so the benefit of holding the decoded instruction is obvious.
In this project the students will design a RISC CPU and implement a decoded instruction cache. The design will include and artificial delay in the decode operation, such that the performance improvement can be demonstrated.
Notes :
1. The design will be implemented in SystemVerilog
2. Students will have to demonstrate the CPU operation by developing some assembly code to be executed.