Design of an RSA Public-Key Encryption Processor

The RSA algorithm stood out among asymmetric encryption systems as a conceptually simple and practical encryption and authentication method which provides a near perfect level of security.
Public-key cryptographic systems, such as the RSA often involve modular exponentiation (Z = Ye mod n). This widely used and computational complex operation is  performed using successive modular multiplications (C = AB mod n).
The performance of such cryptosystems is primarily determined by the implementation efficiency of modular exponentiation .
Creating a hardware system compute this operation has many performance benefits.  One new possibility would be to use the public-key system  for the actual communication rather than only communicating the keys of a symmetric system.
In this project we will research the different techniques and approaches for fast modular arithmetic and build an optimized hardware processor.

It is expected of the students to devote no more than 20% of the effort to the algorithmic part of the system, and 80% to the hardware implementation.

Since the architecture is special purpose and quite unique, the usefulness of automated tools may at times be limited and in these cases we will have to hand design entire circuits at least at the block level.

The selected architecture will be designed and implemented in SystemVerilog or VHDL. Simulations will be performed to verify correct functionality. Finally, the design will be synthesized and the layout implemented.

Automated tools will be used (behavioral code) mixed with hand design where necessary to implement optimized functions.

In this project you will learn about encryption system, architectural VLSI design, efficient RTL implementation, synthesis and layout


Prerequisites: Logic Design