Accelerator for GNSS Acquisition and Tracking

An advanced Global-Navigation-Satellite-System (GNSS) accelerator, which provides the end user with improved position, velocity and time solutions.
High performance conventional GPS/GNSS receivers rely on ASIC technology to implement massive correlators, as the performance of SDR solutions is still limited. With a reasonable distribution of tasks between the host hardware and reconfigurable peripherals, a higher performance is achieved.
The figure illustrates a schematic structure of a GNSS receiver, where the proposed project targets only the “Acquisition & Tracking” module.
Design goals and challenges
Learning the basics of Verilog RTL coding language (commonly used in the industry).
Learning the basics of communication protocols, hereby AMBA APB.
Learning common GNSS standards which are commonly used in the industry.
Practice in coding design using arch. spec., ramping up an advanced accelerator as an IP.
This project suggests building a designated acceleration IP, which performs GNSS Acquisition & Tracking calculations and thereby dramatically offloads software with navigation applications. The IP reads the digital IF (after ADC) data, performs the correlation-based calculations and writes the results into a local SRAM. The IP is triggered by software Host through APB registers, and interrupts back the host when calculation is completed.