The first steps in the physical design of VLSI chips are partitioning and floorplanning. Partitioning is the process of dividing the chip into smaller pieces so that each piece is easier and faster to run. Floorplaning is the process of providing a shape to each piece so that the sum of the pieces is the entire chip and there are no overlaps
The object of this project is to perform the process of floorplanning of a chip by dividing each piece into smaller sub-pieces and using a placement algorithm on the entire “chip”.
After the placement – the sub-pieces should be merged into the final shape of the larger pieces.
Floorplanning is a crucial process in VLSI design. Usually it is performed by optimizing the traditional design metrics, i.e., chip area and total wirelength. In addition, as technology advances, many other design constraints and objectives must be considered in modern floorplan designs. This makes it much more difficult to design effective algorithms for obtaining high quality floorplan results.
In the paper below, in order to handle a multi-objective thermal-aware non-slicing floorplanning problem efficiently, an adaptive hybrid memetic algorithm is presented to optimize the area, the total wirelength, the maximum temperature and the average temperature of a chip.
The goal of this project is to implement a floorplanning tool based on the described algorithm.
An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning, Jianli Chen, Yan Liu, Ziran Zhu, Wenxing Zhu
Prerequisites: Any programming language with ability to learn new concepts quickly