Improvement of Power/Performance in RSA Encryption Using CNFET Technology

Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy–delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies.

In order to evaluate the potential of CNFETs to replace silicon CMOS technology, SPICE models of CNFETs have been developed. One such model was also tested in our VLSI lab and found to be compatible with our Virtuoso simulation tool for design.

RSA encryption is one of the most widely used algorithms for encryption. In RSA encryption very large adders (1024 bits and more) are needed for many stages of the computation. Implementing efficient (low power/high speed) adders would provide a significant increase of performance.

Project Requirements:

In this project, the students will design and simulate CNFET-based RSA encryption adder architecture. The students will study different adder architectures for RSA encryption and choose the best one for CNFETs implementation. The students will learn about CNFET properties and compare the CNFET technology with CMOS technology with an emphasis on high speed and low power consumption.

Prerequisites: Electronic Switching Circuits (044147) & Digital Systems (044145 or 234145)