The Bose, Chaudhuri, and Hocquenghem (BCH) codes form a large class of powerful random error-correcting cyclic codes. This class of codes is a remarkable generalization of the Hamming code for multiple-error correction.
BCH codes are used in varied applications such as satellite communications, compact disc players, DVDs, disk drives, solid-state drives, two-dimensional bar codes, SRAMs, etc.
This project proposes building a designated BCH IP core, which can be configured to perform either BCH encoding or BCH decoding in real-time conditions. The IP (intellectual property) will have 3 main interfaces: BCH channel, SRAM and APB. It will support a flexible in/out configuration, i.e. handling dataflow in both direction, e.g. Channel-to-SRAM or SRAM-to-Channel. The IP is triggered by the host software through APB registers, and interrupts back the host when calculation is completed
Design goals and challenges
- Learning the basics of Verilog RTL coding language (commonly used in the industry).
- Learning the basics of communication protocols, hereby AMBA APB.
- Learning common coding standards which are commonly used in the industry.
- Practice in coding design using arch. spec., ramping up an advanced accelerator as an IP.
- AMBA APB – http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0024c/index.html
- BCH (+intro):
- FEC (wiki): https://en.wikipedia.org/wiki/Forward_error_correction
- Hamming (wiki): https://en.wikipedia.org/wiki/Hamming_code
- BCH (wiki): https://en.wikipedia.org/wiki/BCH_code
- ProductRef: http://www.china-core.com/upload/1499071198cbe685cde917ae9e91c1932a194b6cdc.pdf
Prerequisites: Logic Design