3D Flash Memory Management

Recently introduced 3D vertical flash memory is expected to be a disruptive technology since it overcomes scaling challenges of conventional 2D planar flash memory by stacking up cells in the vertical direction. New 3D flash memory enables to increase storage capacity and has improved endurance. However, there are unique issues that require proper controller management. Such issue is the “fast detrapping” which is a fast charge leakage from the isolation layer that leads to data errors.

In this project, we will design an algorithm to detect and correct such errors. The scheme relies on a coding technique that incorporates the side information of fast detrapping during the encoding stage. The implementation includes matlab modeling, spec and architecture definition, logic design using the Verilog HDL, verification and synthesis. The emphasis of this project will be on low gate count of the design.

Project goals:

· Understanding of modern error-correction algorithms and coding theory background.

· Architecture development, logic design, implementation in verilog HDL, simulation, synthesis and layout.

Prerequisites: Logic Design