Design and implementation a Posit Arithmetic Unit supporting posit new format focusing on the stages of regular VLSI design process, namely architecture, HDL implementation, simulation, synthesis and layout.
Hardware implementation of Floating Point Units (FPUs) has been considered an issue of major importance in a processor design due to their massive area and complexity. Nowadays, most FPUs designs implements IEEE-754 standard which specifies the format and the architectural behavior of floating point numbers. Recently, a proposal to replace IEEE 754 compliant FPUs, named Posit Arithmetic Units (PAUs), have been suggested.
Posit provides important advantages over floating point numbers, including larger dynamic range, higher accuracy, bitwise identical results across systems, simpler hardware, and simpler exception handling[1].
In this project, you will design and implement a Posit Arithmetic Unit supporting posit new format focusing on the stages of regular VLSI design process, namely architecture, HDL implementation, simulation, synthesis and layout.
Prerequisites:
- Logic Design, Computer Architecture (advantage)
Comment: A research oriented project
Main supervisor: Yossi Jose Yallouz
[1] J. Gustafson and I. Yonemoto, “Beating floating point at its own game: Posit arithmetic,” Supercomput. Front. Innov.: Int. J., vol. 4, no. 2, pp. 71–86, Jun. 2017. [Online]. Available: https://doi.org/10.14529/jsfi170206