Power-Aware Clock Tree Synthesis 

Clock is the crucial component of any modern VLSI circuit. Clock distribution network is usually has a form of a mutli-stage buffer tree with main clock driver at the root and clock consumers (sequential elements – flip-flops and latches) at leafs. The process of creation of the clock tree is called Clock Tree Synthesis (CTS) and it is very important stage in VLSI design process. The CTS problem can be defined as follows: given locations of the clock consumers, find optimal number of stages and locations of the clock buffers, so that the delays from root to leaves meet pre-defined values. Except for delay, another important aspect of the modern design, and especially of the clock tree, is power. Thus, not only should the synthesized clock meet delay constraints but also consume as little power as possible. In this project, the students will learn and implement a simplified algorithm for power-aware clock tree synthesis. The algorithm further can be explored on real design case.

The project includes:
– Implementation of simple GUI for reading initial data and representing results.
– Implementation of the power-aware clock tree synthesis algorithm.

Prerequisites: Programming in C++ in UNIX environment. Any course on data structures and algorithms.