Implementation of a Smallest Univalue Segment Assimilating Nucleus (SUSAN) Block

Edge and feature extraction is one of the most important first steps in computer vision. Its main objective is to find as many useful features from a scene while keeping the output noise level to a minimum. Edge, corner and vertex detection processes serve to simplify the analysis of images by drastically reducing the amount of data to be processed.
 The SUSAN principle is the basis for algorithms to perform feature extraction. Papers on SUSAN have been published in BMVC92, ICPR96 and IJCV, and a patent has been granted. Algorithms based on Susan have the potential of achieving a better performance and a lower computational demand than other well known methods. A complete description and demos of SUSAN can be found here.
The goal of this project is to develop a variation of the SUSAN algorithm which can be implemented with digital processing on special purpose hardware.  The goal of this algorithm will be focused on corner detection.
Initially, the algorithm will be implemented in a high level language (C or matlab). Next, an efficient architecture is to be designed which will then be implemented in VHDL or Verilog. The HDL language implementation will be simulated, synthesized and the final layout will created with an automatic place and route tool.
 The design requirements are:
- A pipelined architecture for maximum throughput
- A minimal amount of on chip memory for temporary storage for minimum chip area
- Full verification according to test image.

Prerequisites: Logic Design