Fast Gain-Cell Design for eDRAM-centric Design

The need for SRAM replacement This proposal aims at replacing SRAM technology by Gain-Cell (GC) Embedded DRAM (eDRAM) in processors design. While the demand for on-die storage is increasing, the supply voltage has reached deep sub-volt level, where SRAM cells are susceptible to data corruption and information loss. Increasing the supply voltage is out of consideration since it causes dramatic increase in power consumption. We suggest replacing SRAM by GCeDRAM, which is CMOS logic compatible, thus has low manufacturing cost. GC was designed to achieve a small area and power. It avoids the read-refresh required in ordinary 1T1C eDRAM.
 
There are several types of GC comprising two, three and four transistors, which have an order of magnitude less leakage-power and occupy less than half of the area of a 6TSRAM cell. GCs have two separate ports. This enables the design of memories supporting simultaneous read and write. The main drawback of eDRAMs compared to SRAMs is their refreshing requirement, due to leakage at its storage node. GC Data Retention Time (DRT) can vary from a few to hundreds of microseconds, depending on the memory cell structure and the technology in use.
Another important aspect is the speed of reading GC. While most of the literature proposed single ended cells, suitable for near-gigahertz applications, this may be insufficient speed for multi-gigahertz processors. For this sake GC should be enhanced towards differential operation mode. As in SRAM cells, it should have both bit and its complement read ports, which will require circuit re-architecture. Clearly, more transistors will be involved in GC, which may have a dramatic effect on the array area efficiency and power consumption. The tradeoffs between differential GC area and speed must be studied. This project aims at designing a differential GC, at the mask level, including SPICE simulations from extracted layout. Few circuit configurations will be studied.