The goal is to implement a generic system that is allowed to add input queues, output queues, with different parameters in enqueueing/dequeueing elements to/from their queues.
Network routers by nature handle thousands of mega packets per second. Each packet might come from one port and be destined to another port. The actual routing decision is made only once the packet is received and inspected.
This scheme by definition, causes head of line blocking, in which one packet destined to a blocked destination completely blocks the input queue or the common processing pipeline. These kinds of problems are commonly analyzed and solved by different techniques in the industry.
In this project, the student is required to perform the following tasks:
1) Survey the academic literature for existing solutions
2) Theoretically analyze several possible solutions
3) Select 2-3 solutions with justifications
4) Model the selected, using high level language (C++, System C , etc.)
5) Refine the solution based on some synthetic data gathered for this analysis.
6) Decide which option to use.
7) Algorithm implementation should be done in VHDL/Verilog using the C model as the reference model for simulation.
Project requirements (implementation phase)
1) Implement generic system that is allowed to add input queues, output queues, with different parameters in enqueueing/dequeueing elements to/from their queues.
2) Run simulations to demonstrate the potential problems in normal ‘Round Robin’ arbitration between input queues.
3) Design an arbiter which is aware of intermediate data congestion on the output queues.
4) Perform simulations to demonstrate the overall performance improvement.
The report should include static analysis of the system, as well as dynamic analysis of the system before and after the arbitration improvement.
Prerequisites: Logic Design
For more information, please contact Goel Samuel Room 711 Mayer Building, tel 4668, firstname.lastname@example.org
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