As the demand for high throughput increases for applications like HD 4K, VR glass, signal processing in autonomous car, a high speed chip to chip interface become a bottleneck for data transfer between components. Few examples includes RF front end communication with the application processor SOC, FPGA accelerator communications with display chip/memory, high definition 3D camera communications with DSP chip and more. In order to support the high data throughput, the frequency of the chip to chip interconnect increases, and accordingly the number of on board traces increase as well. This leads to more complex and expensive boards and silicon designs. One way to solve the problem, is by designing a very fast SERDES (Serializer/Deserializer) on differential lines, which supports high frequency bandwidth.
This project will focus on development of a high speed/high bandwidth SERDES receiver amplifier, which needs to handle a small input signal while maintaining signal quality and converting it to CMOS signal (logic levels) without affecting the transmitted data. The data rate target is to reach 10Gbps with a minimum amplitude swing of 100mV peak to peak.
The student will focus on the following tasks:
• Learn the principles of small signal amplifier (two gain stage)
• Explore different architecture for high bandwidth amplifier, pros and cons
• Understand design spec requirements and design the amplifier based on spec
• Understand how process and layout (LO) affect on the design, and suggest method to overcome the process/LO constraint
• Understand how to model a transmission line
• Design and simulate amplifier on a model of transmission line.
• Build Layout of the amplifier, and see how it impact the amplifier performance.
Prerequisites: Linear Circuits