Projects

Description.

  • Cloud Data Reduction Processor

    The design and implementation of a low-power dedicated processor that will be integrated into the storage system and in order to reduce as much as possible the volume of the data needed to be stored in the storage system.

  • The Development of a JTAG Boundary Scan Structure for VLSI Chips

    Many techniques have been developed to simplify the testing of device after production. One technic is called "boundary scan" or sometimes referred to as "JTAG" (Joint Test Action Group). Each device that complies with the standard, which was accepted by the IEEE, includes 5 dedicated pins for testing only (AKA TAP – Test Access Port). In this project the students will take an existing logic project, preferably their own VLSI...
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  • AXI Bus Scaler

    The idea is designing an AXI bus down-sizer (for Read and Write transactions) from any (power-of-two bits) data width source to any (power-of-two bits) data width target, while maintaining (1) the integrity of the transactions, (2) the full data rate (enforced by the narrower side of course) for a predefined outstanding transactions level, and (3) the best optimization accessing any endpoint IP.The project will address AXI3, AXI4, AXI5 flavors (same...
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  • Continuous Time Linear Equalization (CTLE) Circuit Implementation

    In the wake of the growing amount of data being processed in data centers, it is necessary to send the data at increasingly higher speeds. The goal of this project is to build a modern high-speed link that can process data at a rate of 25Gb/s. Basically, the link sends data from a transmitter to a receiver. The straightforward solution of data transiting into a simple wire between those two...
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  • Hardware Accelerator for a Machine Learning Naive Bayes Classifier

    Project description: A classifier is a machine learning model that is used to distinguish between different objects based on features. The Naive Bayes classifier is very effective in many real-world situations, like document classification and spam filtering. A Naive Bayes classifier is based on applying Bayes’ theorem. It utilizes the “naive” assumption of conditional independence between every pair of features.  Despite this simplifying assumption naive Bayes classifiers work very well....
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  • On-Chip Temperature Sensors

    An accurate, small, low-power CMOS temperature sensor for on-chip thermal monitoring will be designed and analyzed in this project. The temperature sensor utilizes the temperature characteristics of the threshold voltage of a MOS transistor to sense temperature and is quite linear over the in-temperature range (-20C, 100°C). Mixed signal, switch capacitor based architecture will be analyzed during evaluation study and implemented in 28nm technology. The circuits will be designed under...
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  • Flash Memory Controller Block

    Flash memory is widely-used memory technology, used in disk-on-keys, SSDs, set-top boxes (routers, TVs etc.), cellular SIM, and more. Flash memory requires a unique memory controller, as Flash is block-addressable, has unique error handling correction properties, wear leveling management and more. Solid-state drive architectures can arrange Flash chips and controller in several topologies: channels, bus-based, full crossbar and more. In this project, the students will implement a design of controller...
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  • Error Correction/RAID Engine for DNA-Based Storage

    Project description: DNA digital data storage is defined as the process of encoding and decoding binary data to and from synthesized DNA strands. The global community produces digital data at increasing rates, creating enormous data centers for storage. Recent research proposes replacing the traditional data storage devices with biological DNA-based device, which can store information of the scale of a data-center within a few grams of weight. During DNA synthesis...
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  • Low Voltage CMOS Based Band Gap Circuits

    This project deals with design and optimization of low voltage band gap reference circuits, based on 28nm TSMC technology. In this project several low voltage band gab architectures will be analyzed during an evaluation study and the results will be compared. The circuits will be designed under required performance constraints of minimal power, layout area, signal cross talks and noise reduction using advanced IC technologies. The students will be responsible...
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  • DNA Memory Enhancement using Signal Processing

    Project description: DNA digital data storage is defined as the process of encoding and decoding binary data to and from synthesized DNA strands. The global community produces digital data at increasing rates, creating enormous data centers for storage. Recent research proposes replacing the traditional data storage devices with biological DNA-based device, which can store information of the scale of a data-center within a few grams of weight. During DNA synthesis...
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  • Implementation of Randomised Modular Exponentiation

    In this project we will implement the technique of randomized exponentiation as a measure against side channel attacks. This approach achieves masking at the algorithmic level rather than utilising arbitrary circuits.

  • Probability Solver for Combinatorial Circuits

    In this project we will seek to answer questions such as the following: conditioned on the event that the output of the circuit is true, what is the probability that the 7th input value is false?

  • Implementation of an LOTR RISC-V Based System on Chip (SOC) on an FPGA

    Project description: This project will focus on the implementation of an “Embedded System” which includes a System Verilog SOC design with cores, memory, accelerators, NOC (network on chip) etc. The students will work on FPGA Altera devices on which they will implement the LOTR-RISC-V fabric. Using the MMIO(Memory Mapped IO) UART/TAP interface the student will enable the FPGA to communicate with the computer via terminal and Python scripts. This project...
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  • Exploring Analog Noise Effect on Deep Learning Applications

    Background information: Recently, several different memristive technologies (ReRAM, CBRAM, PCM and STT-MRAM) have emerged as promising candidates for digital and analog in-memory computation. Deep neural networks (DNNs) are one of the main application to benefit from analog in-memory computation. However, the noisy nature of analog computation may let to performance (“accuracy”) degradation. In this project, you will use IBM analog hardware acceleration kit, a kit developed by IBM to simulate...
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  • A Hardware Accelerator for Unsupervised Learning Based on a Gaussian Mixture Model

    Clustering is the task of dividing data points into a number of groups such that data points in the same group are more similar to other data points in the same group than those in other groups. Kmeans is an effective clustering algorithm based on clustering the data points using the minimum distance of the mean of all the points in each cluster. For some datasets, Kmeans does not provide...
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  • Unique Algorithmic Paradigm of Processing-in-Memory

    Background: Processing-in-memory (PIM) solutions unite computation and memory to overcome the memory-wall, while also introducing ample opportunities for high-throughput operations. Memristive processing-in-memory is based on the memristor: an emerging fundamental device that is capable of both storage and logic by representing binary information through resistance. Efficient utilization of processing-in-memory requires rethinking many aspects of computing systems, including novel algorithmic techniques that can utilize the high-throughput of PIM.   Algorithmic Paradigm:...
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  • Characterization of Speed and Energy of Superconductive Logic Circuits

    Introduction: Recently, power dissipation is becoming a dominant factor in choosing the next technology. For this reason, most figures of merits currently used to test the potential of a given technology to be the next leading technology in the industry are Operations/Second x Watt or Joule/bit….and not just Operations/Second. Superconductivity is the phenomenon in which we have zero DC resistance and is viewed as a technology capable of achieving better...
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  • On-Chip CMOS RF Power Detector

    Emerging mm-wave systems, such as the 5G new radio, will be implemented as phased arrays (multiple transmitters and receivers channels connected to an array of antennas) integrated in CMOS chips. RF CMOS circuit excels in the integration of complex circuits but suffer from a degradation in performance due to mismatches between devices originating in the fabrication process. As matching between the channels is critical for the array performance, calibration circuits...
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  • Convolutional Deep Belief Nets Based on Memristive Devices

    Project description: Deep neural networks can be extraordinarily accelerated by using memristive devices as synaptic connections. However, traditionally, the deep neural networks utilize the error backpropagation algorithms, which face some issues when the networks are implemented in hardware based on memristive devices: i) complex peripheral circuits with expensive ADCs and DACs and memory back for intermediate layer states; ii) lack of efficient online training methods. We recently developed an efficient...
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  • Novel Synthesis and Mapping of RRAM-based Stateful Logic on 3D RRAM

    Background: Computing-in-memory (CiM) has been a potential solution to break the memory wall and energy wall brought by the conventional computer architecture that separates the computing units and memory units. RRAM-based stateful logic is a kind of CiM that could implement any function in RRAM crossbar array. There are some efficient synthesis and mapping methods for 2D RRAM crossbar array. 3D RRAM crossbar arrays are denser and can support stateful...
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  • Approximate Search CAM for DNA sequencing and Genome Analysis

    Project description: How can we tell when a new mutation of COVID virus appears? We sequence DNA samples from many patients. These samples contain the host (patient’s) DNA as well as DNAs of multiple viruses and bacteria that live in our body and make their way to the sample. Then, we need to compare huge amounts of sequenced data with existing COVID strains and decide if there is a new...
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  • Hardware Acceleration of Local Sensitivity Hashing for Genome Assembly

    Project description: High-throughput sequencing have substantially changed the way biological research is performed since the early 2000s.  These sequencing technologies obtain millions of short fragments (sequences) of DNA from a living organism to generate the organism’s DNA blueprint (genome). Thanks to these new DNA sequencing platforms, we can now investigate human genome diversity between populations, find genomic variants that are likely to cause diseases and even investigate the genomes of...
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  • Hardware Implementation of a Video Processing Superblock Accelerator

    Project description: Background: The goal of the project is to design and implement a video processing accelerator to allow real time processing of a video stream. The accelerator will be composed a series of independent video processing units each of which receive a video stream as input and generate a processed video stream at the output which is fed into the next unit. Alpha blending is the process of combining...
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  • Hardware Implementation of the Video Polynomial Transformation + LPF

    Project Abstract: There are endless number of platforms that require implementation of video transformations, such as curve TV/computer/smartphone screens, goggles, pilot hamlet, etc. All these platforms require transformation of flat image to curved image that fits the display, so the user can see the image well without data loss. The main challenges of the core implementation are low latency (“video in => video out), high video resolutions and frame rate....
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  • Hardware Acceleration of DBSCAN Clustering

    Project description: Clustering is the task of unifying data points into groups or clusters, where the grouping of the points is commonly based as distance. Clustering has many applications including data mining, statistical data analysis, pattern recognition, and more. Two common clustering algorithms are K-Means and Density-Based Spatial Clustering of Applications with Noise (DBSCAN). With increasing needs to perform clustering on large datasets as fast as possible, running these on...
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  • Accelerator for DNA Sequence Alignment

    Project description: One of the most popular operations in personalized medicine is protein or DNA sequence database search based on pair-wise alignment, where a query sequence is compared with a database of sequences to find a highest-similarity sequence. This similarity can provide insights on the functionality of the query protein or the role of a gene. Conventional computer architecture is proven to be inefficient for personalized medicine tasks. For example,...
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  • Modeling of Biological Processes using Subthreshold Analog Circuits

    The ability to reliably and quickly model the behavior of basic biological processes may allow future analysis of complex biological systems and the use of models for drug research and development. As equations describing transistor operation below the threshold voltage and equations describing chemical reactions have significant similarities, analog circuits can be designed to model biochemical reactions and biological processes. In cytomorphic engineering the cellular behavior of biological systems is...
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  • Switched Capacitor 6th Order Filter

    In the 1970s, CMOS technology was finding its way into analog design through switched-capacitor circuits. The availability of simple switches and high impedance nodes in CMOS afforded more efficient sampling and holding of signals than in bipolar technologies. Most of the high-performance filters, sigma-delta modulators, and data converters are based on switched-capacitor (SC) techniques. In this project, you will study the operation and design properties of op-amps, bias circuits, integrators...

  • The Design and Implementation of a a Programmable Address Decoder

    A conventional address decoder is conceptually based on a multi-input AND gate that selects a memory row. A unique address of a memory row is set by hardwiring the direct and inverted address bits to the inputs of the AND gate. In a decoder position where the input address matches the hardwired pattern, the AND gate outputs ‘1’, selecting the memory row. The address of a memory row is permanently...
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  • The Design of a RISC-V Minimal RV32I/E Core

    RISC-V is a classic RISC architecture rebuilt for modern times. At its heart is an array of 32 registers containing the processor's running state, the data being immediately operated on, and housekeeping information. RISC-V comes in 32-bit and 64-bit variants, with register size changing to match. The goal of this project is to study the RISC-V instruction set and then to design and implement a minimal RV32I/E Core that supports...

  • The Design of a Ring Controller to Support a Multi-core RISC-V Implementation in a Ring Configuration

    The goal of this project is to design and implement an RTL IP (System Verilog) that will enable multiple instances of RISC-V cores to be connected in a ring configuration. The IP will consist of two main interfaces – on the one side the “Core” and the other the “Ring”. The Ring Interface will manage the data transactions on the ring - pushing and pulling RD/WR/RD_RSP transactions to/from the ring....
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  • HW Implementation of MiniBatch Kmeans – A Clustering Algorithm for Unsupervised Learning

    Clustering for unsupervised learning is an common task in machine learning systems. Several algorithms can be used for this task, for example K-Means. The main problem with K-means algorithm is the huge amount of computations. Minibatch Kmeans proposes an effective technique to drastically reduce the number of computations with an insignificant impact on the quality of the results.  The goal of this project is to design and implement a hardware...
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  • Code Optimizer Using Advanced Matrix Extension

    The Advanced Matrix Extension (AMX), a new x86 extension designed for operating on matrices with the goal of accelerating machine learning computations. Intel’s Advanced Matrix Extensions (AMX) is a new 64-bit programming paradigm consisting of two components: A set of 2-dimensional registers (tiles) representing sub-arrays from a larger 2-dimensional memory image and an accelerator that is able to operate on tiles. In the first stage of this project, a preprocessor...
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  • Implementation of a DNA Sequencing Accelerator

    The DNA Sequencing process involves passing a strand of DNA through the nanopore which causes drops in the electric current passing between the walls of the pore. The amount of change in the current depends on the type of base passing through the pore. This signal is then sampled. In this project, we will design a stand-alone accelerator for the 3rd generation DNA sequence basecalling for personalized medicine applications.
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  • CNT Centric Optimization of CNFET Based Technology in Small Digital Integrated Circuits

    Background: Single-wall semiconducting carbon nanotube (CNT) field-effect transistors (CNFETs) have been among the foremost candidates to complement Si and extend CMOS technology scaling to sub-10-nm technology thanks to the atomically thin body of CNTs and their near-ballistic transport. However, non-deterministic control over CNT chirality and various devices non-idealities (such as high contact resistance (Rc), parasitic capacitance and tunneling leakage currents) can hinder the realization of true CNFET based integrated circuits....
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  • Deep Learning Based Controller for SSD Acceleration

    Project description: Flash memory is widely-used memory technology, used in disk-on-keys, SSDs, set-top boxes (routers, TVs etc.), cellular SIM, and more. Flash memory requires a unique memory controller, as Flash is block-addressable, has unique error handling correction properties, wear leveling management and more. Solid-state drive architectures can arrange Flash chips and controller in several topologies: channels, bus-based, full crossbar and more. There are several new trends in SSDs that should...
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  • The Design of A Secure (Oblivious) Memory

    A standard solution to memory security is encrypting all data written to untrusted storage. A big problem with client-side encryption (and other systems that protect only the data itself) is that it does not protect all aspects of how the client interacts with the server's storage. Where storage is accessed, the access pattern can also reveal secret information. Suppose a patient stores his/her genome on a remote server and wishes to check...
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  • Low Voltage CMOS Based Thermal Sensor Circuits

    In this project some alternative low voltage thermal sensor circuits architectures will be analyzed during an evaluation study and the results will be compared. The circuits will be designed under required performance constraints of minimal power, layout area, signal cross talks and noise reduction using advanced IC technologies.
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  • Delta Sigma ADC Architecture for CMOS Image Sensor

    Project description: This project involves the design and optimization of ∆∑ ADC Architecture for CMOS Image Sensor based on 0.18um TSMC technology. This work presents a 2 Mpixel, 120 frame/s CMOS image sensor with column-parallel delta-sigma ∆∑ ADC architecture. The use of a second-order ∆∑ ADC improves the conversion speed while reducing the random noise (RN) level as well. The ∆∑ ADC employing an inverter-based ∆∑ modulator and a compact...
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  • Accelerator for Sparse Machine Learning

    Sparse linear algebra is a frequent bottleneck in machine learning and data mining workloads. The efficient acceleration of sparse matrix calculations becomes even more critical when applied to big data problems. The goal is to implement an accelerator for multiplying a sparse matrix with a sparse vector. Current solutions fetch from memory all non-zero elements of the sparse matrix. The aim of this project is to implement a technique in...
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  • Acceleration of Local Sensitivity Hashing for Genome Assembly

    High-throughput sequencing have substantially changed the way biological research is performed since the early 2000s.  These sequencing technologies obtain millions of short fragments (sequences) of DNA from a living organism to generate the organism’s DNA blueprint (genome). Thanks to these new DNA sequencing platforms, we can now investigate human genome diversity between populations, find genomic variants that are likely to cause diseases and even investigate the genomes of even ancient...
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  • Simulation of a Wear Leveling Algorithm

    SSD & Flash memories are memory elements which are based on electron injection to change the properties of the transistor. While this allows for a small memory element which keeps it data even when powered off – this introduces a new problem: After an unknown number of writes – the transistor can malfunction and stop working. The solution to this problem is to keep track on reads and writes across...
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  • Hierarchical Connectivity Model (HCM) For CAD Purposes

    Hierarchical Connectivity Models (HCM) are used to describe hardware designs using high level programming language for implementations of VLSI algorithms and automation tools. With the growing complexity of digital hardware designs (VLSI), the need for automation tools is growing rapidly. In order to implement these tools, an efficient HCM tool which parses Hardware Description Language (HDL) files into an Object-Oriented Programming (OOP) environment is required.   This project purpose is...
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  • Implementation of A Genetic Algorithm for Channel Routing in VLSI Circuits

    Description: The first steps in the physical design of VLSI chips are partitioning and floorplanning. Partitioning is the process of dividing the chip into smaller pieces so that each piece is easier to deal with. Floorplanning is the process of providing a shape and a location for each block. The next step is to optimally place the standard cells within each block and the file step is to perform the...
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  • Wire Activity Estimation for Intelligent Power-Aware Placement

    In modern VLSI technology nodes, most of energy is consumed by wires rather than by gates. However, traditional placement tools optimize for wire delay rather than for wire energy consumption. While optimizing for delay is relatively straightforward (you just need to place components of the same logic function as close to each other as possible), minimization of wire energy is more complicated. It requires an accurate estimation of wire activity...
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  • Design and Implementation of a Hardware Accelerator for Deep Convolutional Auto-Encoder

    An advanced scalable hardware accelerator for deep Convolutional Auto-Encoder (CAE), targets deep-learning applications. Integrating a CAE hardware accelerator has advantages in resources occupation, operation speed, and power consumption, indicating great potential for application in digital signal processing. This project suggests building a designated acceleration IP, which efficiently performs RAM-to-RAM calculations in a pipeline fashion and thereby dramatically offloads machine-learning software applications.
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  • Cellular Nonlinear Network based on Memristive Devices

    In this project, theories of the cellular nonlinear network will be studied and the possibilities of using memristive devices in these networks will be investigated. A software model of prototype cellular nonlinear neural network accounting for the behaviors of memristive devices as the synaptic connections will be implemented and a series of simulations will be performed.
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  • Electromigration-Aware Architecture for Modern Microprocessors

    In this project, we propose a new architecture that significantly improves reliability by reducing EM impact while relaxing the physical design efforts and significantly extending microprocessor lifetime. It is based on the observation that in many cases EM reliability issues result from excessive write activities or signals toggling in a non uniform manner.  We will examine EM improvement to 3 main components of microprocessors: ALU execution unit, register file and...
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  • GUI Implementation and New Features for Bitlet

    The Bitlet model is a new an analytical, parameterized,  modeling tool, developed in the ASIC2 lab. The Bitlet model can be used to estimate the performance and the power of a PIM-based system and thereby assess the affinity of workloads for PIM as opposed to traditional computing.In order to make Bitlet more beneficial, it has to be made more accessible to users by equipping it with new features and interactive graphical...
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  • Systolic Array Acceleration of CNN Per-Channel Activations Quantization

    In this project, you are required to design a systolic array that efficiently implements the logic required to support per-channel activation tensor quantization for a convolution neural network. You are required to implement the design using SystemVerilog, simulate and synthesize it after which the layout will be designed. Area, power, and energy will be analyzed and compared to a conventional systolic array. Skills you will acquire: SystemVerilog, Synopsys Design Compiler,...
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  • Binary Neural Network (BNN) Accelerator Implementation within Ferroelectric Memory Array

    Ferroelectric Field Effect Transistor (FeFET) memory has shown the potential to meet the requirements of the growing need for fast, dense, low power and non-volatile memories.Integrating a layer of ferroelectric within the gate stack of a regular Field Effect Transistor (FET) enables the transistor to store data in the polarization state of the ferroelectric. In this project, we look for appropriate application of binary neural network (BNN) which can benefit...
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  • Logic Effort Based Delay Optimization Algorithms for Carbon Nanotube FET Technology

    Recent research in nanoelectronics has begun exploring the potential of carbon nanotube field effect transistors (CNFETs) as a successor to CMOS. In order to evaluate the potential of CNFETs as an alternative to silicon CMOS technology, SPICE models of CNFETs have been developed. The goal of this project is to develop a smart algorithm, based on logic effort, to design circuits more efficiently for delay optimization.
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  • Hardware Implementation of the Video Polynomial Transformation

    There are endless number of platforms that require implementation of video transformations, such as curved TV/computer/smartphone screens, goggles, pilot hamlet, etc. All these platforms require transformation of flat image to curved image that fits the display, so the user can see the image well without data loss. The main challenges of the core implementation are low latency (“video in => video out), high video resolutions and frame rate. The goal...
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  • Detection of Hardware Trojan Horses

    Hardware Trojan horses are a real concern for the last 12 years or so, especially for national security. . A few examples of what such a Trojan can do when triggered are : 1. Turn off security protections or insert a known key to the encryption engine; 2. Insert errors to cause malfunction of a critical infrastructure; 3: Leak information to an unprotected zone (for example from a privileged CPU...
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  • Dual Issue RISC-V Processor

    RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university. The goal of this project is to evaluate the enhanced performance of the double issue capability.
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  • Implementation of a Generic Fixed Point Divider

    The goal is to design and implement the HDL of a high-performance hardware serial divider for high frequencies. Initially, at least two different division algorithms will be investigated and analyzed. The design will be parametrized so that it can be configured according to specified requirements. The divider will support a variety of input / output number representation formats.
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  • Identifying Datapaths in a Gate Level Netlist

    Logic designs is usually comprised of two types of logic: data paths and control logic. During reverse engineering, we first try to locate the data path structures taking advantage of their regular structure. Finding these structures helps in locating major circuit elements, such as register files, adders, ALU, multipliers, etc. The distinguishing property of data paths is aggregation of bit-level operations into multibit word operations. In this project, we will...
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  • Implementation of Partitioning for Placement of a VLSI Design

    Decomposing a system into two or more smaller parts which are relatively independent can be very useful in solving a wide variety of problems. This decomposition is called partitioning. Placement is the process in which layout blocks of a VLSI design are placed at “optimal” locations in order to minimize some cost function. The first stage of a placement algorithm involves the efficient partitioning of the design into many smaller...
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  • Risc-V Based Emerging Memory SW Emulator – System Design

    Recently many novel memory technologies are emerging. For example ReRAM, STT-MRAM, DRAM. All these technologies are very suitable for  in memory processing. Unfortunately, at the present time, there  are no actual devices and so simulating in-memory processing with these technologies is very difficult. The goal of this project is to provide a model which can be used to perform these simulations.
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  • Risc-V Based Emerging Memory SW Emulator

    Recently many novel memory technologies are emerging. For example ReRAM, STT-MRAM, DRAM. All these technologies are very suitable for  in memory processing. Unfortunately, at the present time, there  are no actual devices and so simulating in-memory processing with these technologies is very difficult. The goal of this project is to provide a model which can be used to perform these simulations.
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  • Accelerator for ZNCC-Based Template-Matching

    Project description:Template Matching is a method for searching and finding the location of a template image in a larger image. It relies on calculating at each position of the image under examination a correlation or distortion function that measures the degree of similarity or dissimilarity to a template sub-image.Among the correlation/distortion functions proposed in literature, Normalized Cross-Correlation (NCC) and Zero mean Normalized Cross Correlation (ZNCC) are widely used due to...
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  • Memristor-based Multi-Band RF Power Amplifiers

    In this project a tunable power amplification stage will be designed and evaluated. Both stabilization techniques and matching networks will be implemented by memristor-based circuits. The project is based on advanced research. The implementation will be done in Virtuoso and/or ADS.
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  • The Implementation of a Switched Capacitor Integrator

    In this project some alternative SC Integrator architectures will be analyzed during an evaluation study and the results will be compared. The circuits will be designed under required performance constraints of minimal power, layout area, signal cross talks and noise reduction using advanced IC technologies.
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  • Designing New Artificial Atoms by Manipulating Laser Pulses

    Designing New Artificial Atoms by Manipulating Laser Pulses

    New breakthroughs in physics now enable us to shape the quantum wavefunction of electrons. The goal of this project is to design new artificial atoms by using specially designed laser beams that confine electrons into novel bound states, allowing us to control their quantized energy levels. Furthermore, by shaping the electron wavefunction we can cause these atoms to have properties that are impossible with conventional atoms. For example, to create...

  • Design Exploration of Phase-Change RF Switches

    In this project, the RF model of the indirectly heated four-terminal PCM RF switch will be improved and verified against experimental data. The model will be unified with an electro-thermal model of the device to perform optimizations of the device structure for different applications. This model will be used to explore the design constraints of these devices and to find the optimum device geometries for different applications.
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  • Interconnect Stage Calculator and Visualizer

    The performance of integrated circuits is one of the most important design objectives in modern VLSI design. Because of very high frequencies of today’s VLSI circuits, state-of-the-art timing analysis and simulation tools should perform delay and slope calculations with very high accuracy. For this, the timing analysis tools should have two main abilities: 1) stage (cell + interconnect it drives) delay modeling and 2) methods for delay / slope propagation...
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  • AES Add-on Processor for RISC-V

    RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university. RISC-V, pronounced 'Risk-Five', is a new architecture that is available under open, free and non-restrictive licences. It has widespread industry support from chip and device makers, and is designed to...
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  • UVM Verification of an OFDM Transmitter Core

    Project description: Orthogonal Frequency Division Multiplexing (OFDM) is a Frequency Division Multiplexing (FDM) technique used as a digital multi-carrier modulation method. Instead of using one high speed channel, the data is split into a large number of lower speed channels. Orthogonal sub carriers are used to carry data on several parallel data streams which allows more efficient use of the spectrum compare to regular FDM. Orthogonality of the carriers prevents...
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  • Design and Implementation of a Head of Line Blocking (HOLB) Solution

    Problem Description: Network routers by nature handle thousands of mega packets per second. Each packet might come from one port and be destined to another port. The actual routing decision is made only once the packet is received and inspected. This scheme by definition, causes head of line blocking, in which one packet destined to a blocked destination completely blocks the input queue or the common processing pipeline. These kinds...
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  • Loaded-Line Phase Shifters Based on Phase-Change RF Switches

    In this project, a loaded-line phase shifter based on the PCM RF switch that we are developing in our group will be designed and evaluated. Phase shifters are fundamental devices to control the steer the beam in an antenna array and a great number of phase-shifters are required for this critical functionality in 5G and radar systems. PCM RF switches can increase the performance, while reducing the area overhead and...
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  • Implementation of a RISC-V Processor

    RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university. The goal of this project is to study the RISC-V instruction set and then to design and implement a basic RISC-V microprocessor that supports all the instructions. Additional features will...
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  • Controller for DNA-Based Data Storage

    The global community produces digital data at increasing rates, creating enormous data centers for storage.Recent research proposes replacing the traditional data storage devices with biological DNA-based device, which can store information of the scale of a data-center within a few grams of weight.In this project, the student will study the emerging technological approach, and will implement digital controller circuits for managing DNA storage device. The main goals are understanding of...
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  • Backend Implementation of an OFDM Transmitter

    The goal of this project is to perform the complete backend design of the OFDM transmitter chip and its integrated memories. This includes : synthesis, gate level simulation, physical (layout) design and verification, timing verification, power and power grid analysis. The chip may then be submitted for fabrication.  The implementation will be done in Tower CMOS 0.18u technology.
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  • Power/ARM to RISC-V Assembly Converter

    RISC-V is a classic RISC architecture rebuilt for modern times. At its heart is an array of 32 registers containing the processor's running state, the data being immediately operated on, and housekeeping information.  RISC-V comes in 32-bit and 64-bit variants, with register size changing to match. A large amount of code has  been developed and written at IBM in assembly for the PowerPC processor for which no C source-code exists....
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  • Heuristics for Backtracking in SAT

    The goal of this project is to implement, study and experiment with different backtracking heuristics in the winner of the latest SAT evaluation contest (SAT Race 2019). We will try to find a backtracking heuristic, which would improve the performance of the already very efficient solver. It should be noticed that we won’t need to implement any new backtracking algorithm (as the complexity of such an implementation would go beyond...
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  • Implementation of On-Chip Temperature Sensors

    An accurate, small, low-power CMOS temperature sensor for on-chip thermal monitoring will be designed and analyzed in this project. The temperature sensor utilizes the temperature characteristics of the threshold voltage of a MOS transistor to sense temperature and is quite linear over the in-temperature range (-20C, 100°C). In this project some alternative temperature sensor architectures will be analyzed during an evaluation study and the results will be compared.
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  • The Implementation of VCO Circuits

    The voltage-controlled oscillator (VCO) is a critical sub-block in communications transceivers. The role of the VCO in a transceiver and the VCO requirements will be reviewed and the necessity of GHz VCOs and the driving factors towards the monolithic integration of the VCO be examined. In addition, the VCO design techniques will be outlined and design trade-offs be explored.
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  • “Ramanujan Machine” – An Auto-generator of Mathematical Conjectures

    Our group is developing computer algorithms to create a “Ramanujan Machine” – an auto-generator of mathematical conjectures, similar to the role great mathematicians took in the past (Hilberts problems, Fermat’s last theorem etc). Some progress has been done in the last decade about automatic theorem proving (ATP), but to the best of our knowledge, we’re the first to attack the problem of automatic conjecturing with artificial intelligence. This is a...
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  • Hardware Reverse Engineering Analyzer Evaluation

    Reverse engineering of Integrated Circuits (IC's) is a complex process that involves multiple disciplines and skills. The input to the process is usually a physical device, and the output is a human-readable specification. At the first phase, the IC passes tear down to obtain a gate-level netlist description. In the second phase, a specification is extracted. The second stage is non-trivial and involves various learning algorithms and heuristics. The purpose...
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  • Resistive Memory Characterization Infrastructure

    In this project, the students will perform characterization of a Resistive RAM (ReRAM) Crossbar array. They will work with a packaged device that contains a few arrays. The measurement setup will be based on a set of SMUs (Source Measure Units)  and a PC platform that control the measuring equipment. The students will use Python to create a set of tool that allow for automatic parameter extraction from memristive devices...
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  • STT-MRAM Memory Controller: Optimization and New Features

    STT-MRAM writes to a memory array by manipulating electron spin with a polarizing current, performs like DRAM but requires no refresh, significant reduction in switching energy compared to FS Toggle MRAM, highly scalable, enabling higher density memory products (sampling 1Gb in 2019), can interface with JEDEC DDR3 with minor modification, and is  quite an attractive emerging memory. The goal of this project is to implement and simulate circuits using this device.
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  • Implementation of a Performance Widget IP

    Performance aspects are becoming more and more relevant in modern hardware architectures and introduce various engineering challenges in the ASIC domain.Performance plays a central role in both pre-silicon and post-silicon phases and corresponds with embedded-software architecture (e.g. real-time QoS decisions). The performance widget displays data for performance metrics of mobile devices and can be configured to monitor any performance metric. This project proposes designing and implementing a designated Performance Widget...

  • Impact of Input Toggling on the Power for Different MAC Implementations

    A deep neural network (DNN) is an artificial neural network (ANN) with multiple layers between the input and output layers. The DNN finds the correct mathematical manipulation to turn the input into the output, whether it be a linear relationship or a non-linear relationship.Multiply-and-accumulate (MAC) operations are the core of deep neural networks (DNNs). In this project we would like to investigate to what extent the toggling of the MAC...

  • Implementation of a Novel DNN Accelerator with Simultaneous Multi-threading

    A deep neural network (DNN) is an artificial neural network (ANN) with multiple layers between the input and output layers. The DNN finds the correct mathematical manipulation to turn the input into the output, whether it be a linear relationship or a non-linear relationship. The goal of this project is to build a novel DNN accelerator with simultaneous multi-threading.
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