Continuous Time Linear Equalization (CTLE) Circuit Implementation

In the wake of the growing amount of data being processed in data centers, it is necessary to send the data at increasingly higher speeds. The goal of this project is to build a modern high-speed link that can process data at a rate of 25Gb/s. Basically, the link sends data from a transmitter to a receiver. The straightforward solution of data transiting into a simple wire between those two blocks, might encounter some problems, like bandwidth limitation, noise, symbols interference that will deteriorate the original signal. The aim of this work is to build specific tools in the receiver capable of recovering the initial signal and reproduce the original information.

In this project some alternative CTLE architectures will be analyzed during an evaluation study and the results will be compared. The circuits will be designed under required performance constraints of minimal power, layout area, signal cross talks and noise reduction using advanced IC technologies. The students will be responsible for the circuit requirements, analysis and specifications definition, focusing on the readout noise performance. Circuit design and simulations and analog layout will be done using Cadence tools.

Required courses: Linear Circuits
Recommended courses: Introduction to VLSI