Hardware Accelerator for a Machine Learning Naive Bayes Classifier

Project description:

A classifier is a machine learning model that is used to distinguish between different objects based on features. The Naive Bayes classifier is very effective in many real-world situations, like document classification and spam filtering. A Naive Bayes classifier is based on applying Bayes’ theorem. It utilizes the “naive” assumption of conditional independence between every pair of features.  Despite this simplifying assumption naive Bayes classifiers work very well. In addition, Naive Bayes learners and classifiers do not need huge amounts of training data and can be extremely fast compared to more sophisticated methods.

The algorithm utilizes the probabilities of an object to possess particularfeatures in order to perform the classification. A description of the algorithm can be found in:


Project Goal:

The goal of this project is to design and implement a hardware accelerator for the Naive Bayes classifier. In the training phase, all training data will be scanned and all the prior probabilities and likelihoods will be computed and stored in memory. The inference unit will then use these values to perform the computations required for classification. As the computations involve numerous floating point multiplications and divisions, the log2 function and lookup tables (described in the paper below) will be used to simplify and speed up the computations:

A Real-Time Naive Bayes Classifier. Accelerator on FPGA. ZHEN XUE 1,2, JIZENG WEI1, AND WEI GUO1,2

Design goals and challenges

  • Learning the basics of Verilog RTL coding language (commonly used in the industry).
  • Learning the Naive Bayes algorithm.
  • Design and implement an accelerator IP for the Naive Bayes algorithm.
  • Perform the complete VLSI design flow from architectural design to backend implementation of the accelerator using sophisticated Cadence and Synopsys tools.

Prerequisite:  Digital Systems and Computer Structure – 044252