CNT Centric Optimization of CNFET Based Technology in Small Digital Integrated Circuits

Background:

Single-wall semiconducting carbon nanotube (CNT) field-effect transistors (CNFETs) have been among the foremost candidates to complement Si and extend CMOS technology scaling to sub-10-nm technology thanks to the atomically thin body of CNTs and their near-ballistic transport. However, non-deterministic control over CNT chirality and various devices non-idealities (such as high contact resistance (Rc), parasitic capacitance and tunneling leakage currents) can hinder the realization of true CNFET based integrated circuits. Recently, a new data-calibrated compact model for CNFETs which captures dimensional scaling effects, metal-CNT contact resistance, parasitic capacitance, and direct source-to-drain tunneling leakage current, was developed.

Project Description:

In this project the students will learn about CNTs, and about CNT based FETs and their properties. They will design and simulate small CNFET-based integrated circuits using the new model. Then, they will explore in depth the various optimization opportunities and their limits from the realistic CNT centric point of view and compare them to latest CMOS technologies.

Advisor:Michael Shlafman

Prerequisites:Electronic Circuits (044137) or Electronic Switching Circuits (044147) & Linear Circuits (044142)