On-Chip CMOS RF Power Detector

Emerging mm-wave systems, such as the 5G new radio, will be implemented as phased arrays (multiple transmitters and receivers channels connected to an array of antennas) integrated in CMOS chips. RF CMOS circuit excels in the integration of complex circuits but suffer from a degradation in performance due to mismatches between devices originating in the fabrication process. As matching between the channels is critical for the array performance, calibration circuits are integrated into the channels in order to achieve the required accuracy.

Power detection of radio frequency signals is used in many RF applications like power consumption optimization and linearity enhancement of power amplifiers.

In this project we will learn to design an RF power detector, a vital component of any channel for gain calibration and output power measurement. The design will be implemented using an advanced CMOS process such as TSMC 65nm. The detector architecture will be analyzed during the evaluation study and implemented subject to the required performance constraints of minimal power consumption and layout area. The circuit design and simulations and analog layout will be performed using Cadence and Keysight tools.

  • Required courses: Linear Electronic Circuits, Analog Circuits.
  • Recommended courses: Introduction to VLSI, RFIC


Supervisor: Dr. Avi Sayag avi_sayag@hotmail.com