This project involves the design and optimization of ∆∑ ADC Architecture for CMOS Image Sensor based on 0.18um TSMC technology.
This work presents a 2 Mpixel, 120 frame/s CMOS image sensor with column-parallel delta-sigma ∆∑ ADC architecture. The use of a second-order ∆∑ ADC improves the conversion speed while reducing the random noise (RN) level as well. The ∆∑ ADC employing an inverter-based ∆∑ modulator and a compact decimation filter is accommodated within a fine pixel pitch of 2.25 µm and improves energy efficiency while providing a high frame-rate of 120 frame/s.
In this project some alternative ∆∑ ADC architectures will be analyzed during an evaluation study and the results will be compared. The circuits will be designed under required performance constraints of minimal power, layout area, signal cross talks and noise reduction using advanced IC technologies. The students will be responsible for the circuit requirements, analysis and specifications definition, focusing on the readout noise performance. Circuit design and simulations and analog layout will be done using Cadence tools.
Required courses: Linear Circuits
Recommended courses: Introduction to VLSI