The idea is designing an AXI bus down-sizer (for Read and Write transactions) from any (power-of-two bits) data width source to any (power-of-two bits) data width target, while maintaining (1) the integrity of the transactions, (2) the full data rate (enforced by the narrower side of course) for a predefined outstanding transactions level, and (3) the best optimization accessing any endpoint IP.The project will address AXI3, AXI4, AXI5 flavors (same source bus type to same destination bus type, not converting from one to another).
Abstract:
ARM CPU architecture dominates most of the embedded system market segments (including cellular). Routing/Connectivity inside those chips introduce a NIC (network in chip) which usually use one of ARM native bus architectures. As such, most of the IP providers design their interface to meet ARM standard bus terms, for easier integration into those applications. One of those most common bus architectures is AXI (and its flavors). Only, an endpoint IP operating at lower data rates/needs and a CPU or fabric passing heavy data rates, not necessarily use the same bus data-width, which demands to resize the bus and the transactions on their way (usually downsize), while keeping full data rates as possible on that bus system.
Basic/Native converters suggest brute force scaling, but there are sensitive IP’s that are subject to break or loose performance under such boundary conditions.
Project description:
The idea is designing an AXI bus down-sizer (for Read and Write transactions) from any (power-of-two bits) data width source to any (power-of-two bits) data width target, while maintaining (1) the integrity of the transactions, (2) the full data rate (enforced by the narrower side of course) for a predefined outstanding transactions level, and (3) the best optimization accessing any endpoint IP.
The project will address AXI3, AXI4, AXI5 flavors (same source bus type to same destination bus type, not converting from one to another).
Design goals and challenges:
- Studying the ARM AXI architecture and context to its deepest corners.
- Learning System-Verilog RTL coding, and facilitating its capabilities for a flexible and optimized design addressing all the above flavors.
- Analyze, define, and write the specification for such a module.
- Design the module, ramp up a verification testbench and prove performance is kept using simulation. Use standard checkers for proving protocol integrity (by Cadence/Synopsis for example).
- Perform VLSI backend flow (synthesis, place and route, gate count analysis, timing analysis)
- Write a report, identifying all aspects challenged by this mission and how were they solved.
Extension opportunities:
- Extend the design to meet very high frequency by introducing staged (pipelined) approach.
- Extend the design to meet maximum transaction length limitation (enforcing splitting of selected cases).
- Extend the design to meet heavy outstanding demand – introducing proper storage.
Prerequisite: Digital Systems and Computer Structure – 044252
Supervisor : Gil Stoler (Amazon)