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  • רישום למעבדה
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    • חשבון קורס 046265 – סמסטר חורף
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    • חשבון קורס 046918 – סמסטר אביב
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    • חשבון קורס 046237 – סמסטר אביב
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Multimedia and Signal Processors

  • The Design, Fabrication and Testing of an Image Demosaic VLSI Chip

    The goal of this project is to provide the students with a deep knowledge, understanding and experience of all stages of the VLSI design process from concept to the testing of the fabricated silicon. In this project, the students will design and implement a hardware accelerator for an image demosaic algorithm.
    Categories: Backend Design | Digital | Multimedia and Signal Processors
  • Hardware Implementation of a Video Processing Superblock Accelerator

    Project description: Background: The goal of the project is to design and implement a video processing accelerator to allow real time processing of a video stream. The accelerator will be composed a series of independent video processing units each of which receive a video stream as input and generate a processed video stream at the output which is fed into the next unit. Alpha blending is the process of combining...
    Categories: 236381 | Computer Vision | Digital | Multimedia and Signal Processors
  • Hardware Implementation of the Video Polynomial Transformation + LPF

    Project Abstract: There are endless number of platforms that require implementation of video transformations, such as curve TV/computer/smartphone screens, goggles, pilot hamlet, etc. All these platforms require transformation of flat image to curved image that fits the display, so the user can see the image well without data loss. The main challenges of the core implementation are low latency (“video in => video out), high video resolutions and frame rate....
    Categories: 236381 | Computer Vision | Digital | Multimedia and Signal Processors
  • Hardware Implementation of the Video Polynomial Transformation

    There are endless number of platforms that require implementation of video transformations, such as curved TV/computer/smartphone screens, goggles, pilot hamlet, etc. All these platforms require transformation of flat image to curved image that fits the display, so the user can see the image well without data loss. The main challenges of the core implementation are low latency (“video in => video out), high video resolutions and frame rate. The goal...
    Categories: 236381 | Computer Vision | Digital | Multimedia and Signal Processors
  • Implementation of a Generic Fixed Point Divider

    The goal is to design and implement the HDL of a high-performance hardware serial divider for high frequencies. Initially, at least two different division algorithms will be investigated and analyzed. The design will be parametrized so that it can be configured according to specified requirements. The divider will support a variety of input / output number representation formats.
    Categories: 236381 | Digital | Multimedia and Signal Processors
  • הגדרה ומימוש של מעבד מקדים עבור מערכות חישה מרובות סנסורים

    מערכות חישה מתקדמות בנויות ממספר הולך וגדל של טכנולוגיות חישה שונות, כגון - EO/IR/SAR. לכל טכנולוגיה ישנן יתרונות וחסרונות: - למשל מצלמת יום מאפשרת לקבל תמונה ברזולוציה מרחבית טובה מאוד בדו-מימד אך רגישה מאוד לתנאי סביבה ואינה מסוגלת לבצע הפרדה תלת מימדית - מצלמת LWIR) long wave IR) מאפשרת זיהוי אובייקטים בטמפרטורות שונות ורגישותה לתנאי סביבה טובה יותר מאשר מצלמה אופטית רגילה. - מצלמת מכ"ם (SAR) מאפשרת לקבל תמונה בכל...
    Categories: Digital | Multimedia and Signal Processors
  • Implementation of a Smallest Univalue Segment Assimilating Nucleus (SUSAN) Block

    Implementation of a Smallest Univalue Segment Assimilating Nucleus (SUSAN) Block

    Edge and feature extraction is one of the most important first steps in computer vision. Its main objective is to find as many useful features from a scene while keeping the output noise level to a minimum. Edge, corner and vertex detection processes serve to simplify the analysis of images by drastically reducing the amount of data to be processed.  The SUSAN principle is the basis for algorithms to perform...
    Categories: 236381 | Digital | Multimedia and Signal Processors
  • Implementation of a Smallest Univalue Segment Assimilating Nucleus (SUSAN) Block

    The goal of this project is to develop a variation of the SUSAN feature detection algorithm which can be implemented with digital processing on special purpose hardware.  The goal of this algorithm will be focused on corner detection.
    Categories: 236381 | Digital | Multimedia and Signal Processors
    Tags: 3184

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